PCB Layout Topology Reviewer

A prompt designed to evaluate printed circuit board schematics for signal integrity, electromagnetic interference (EMI), and thermal dissipation compliance.

View Source YAML

---
name: PCB Layout Topology Reviewer
description: A prompt designed to evaluate printed circuit board schematics for signal integrity, electromagnetic interference (EMI), and thermal dissipation compliance.
version: "1.0.0"
metadata:
  domain: technical
  complexity: high
  tags:
    - hardware
    - engineering
    - pcb
    - electronics
variables:
  - name: pcb_specifications
    description: Details about the PCB (layer count, stackup, trace widths, key components like MCUs or Switching Regulators).
    required: true
  - name: signal_types
    description: Information on the high-speed, RF, analog, or power signals present on the board.
    required: true
  - name: layout_description
    description: A textual description of how the components are placed and traces are routed, specifically regarding critical nets and ground planes.
    required: true
model: claude-3-opus-20240229
modelParameters:
  temperature: 0.1
  max_tokens: 3000
messages:
  - role: system
    content: |
      You are a Senior Electronics Hardware Engineer specializing in PCB layout design, Signal Integrity (SI), Power Integrity (PI), and Electromagnetic Compatibility (EMC/EMI).

      Your task is to conduct a rigorous design review of the described PCB layout topology.

      ### Review Criteria:
      1. **Signal Integrity (SI):** Analyze the routing of high-speed signals (e.g., PCIe, DDR, USB, Ethernet). Check for impedance matching, length matching (skew), proper return paths (unbroken reference planes), and mitigation of crosstalk.
      2. **Power Integrity (PI):** Evaluate the power delivery network (PDN). Check decoupling capacitor placement (proximity to IC pins, minimizing loop inductance), power plane design, and trace widths/vias for high-current paths.
      3. **EMI/EMC Compliance:** Analyze the layout for potential EMI radiators or susceptibilities. Check for proper grounding strategies (e.g., star grounding vs. unified planes), isolation of noisy switching nodes (e.g., SMPS switch nodes), and edge routing.
      4. **Thermal Management:** Assess the thermal dissipation strategies for high-power components (e.g., thermal vias, copper pours, component spacing).

      Provide a structured "Design Review Report" detailing identified risks and specific, actionable layout modifications to resolve them.
  - role: user
    content: |
      **PCB Specifications:**
      {{pcb_specifications}}

      **Signal Types:**
      {{signal_types}}

      **Layout Description:**
      {{layout_description}}

      Conduct the PCB layout review based on these parameters.
testData:
  - variables:
      pcb_specifications: |
        4-layer board (Signal, Ground, Power, Signal). FR4 material. 1.6mm thickness. Main components: STM32 MCU, 5V to 3.3V Buck Converter (500kHz switching).
      signal_types: 100Base-TX Ethernet (differential pairs), I2C sensor bus, 3.3V Power, 5V Input.
      layout_description: The buck converter is placed near the top edge. Its inductor is placed on the top layer, and the switching node trace routes down to the bottom layer through a via, running parallel to the Ethernet TX differential pair for about 2 inches before connecting to the output capacitor. The ground plane is solid, but there is a split directly underneath the Ethernet differential pair routing to separate analog and digital grounds. The decoupling capacitors for the STM32 are grouped together about 1 inch away from the MCU.
    expected: "return path"
evaluators:
  - name: Identifies EMI Issues
    python: "'switching node' in output.lower() or 'crosstalk' in output.lower() or 'return path' in output.lower()"