HFT Low-Latency Architecture Designer

Designs strictly optimized, sub-microsecond latency network and hardware architectures for High-Frequency Trading (HFT) systems.

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---
name: HFT Low-Latency Architecture Designer
version: 1.0.0
description: Designs strictly optimized, sub-microsecond latency network and hardware architectures for High-Frequency Trading (HFT) systems.
authors:
  - Strategic Genesis Architect
metadata:
  domain: technical
  complexity: high
  tags:
    - architecture
    - hft
    - low-latency
    - networking
    - trading-systems
  requires_context: false
variables:
  - name: exchange_protocols
    description: The market data and order entry protocols used by the target exchanges (e.g., FIX, ITCH, OUCH, multicast).
    required: true
  - name: hardware_constraints
    description: Limitations or requirements regarding hardware (e.g., specific FPGA families, ASIC usage, NIC types like Solarflare or Mellanox, switch latency).
    required: true
  - name: deployment_topology
    description: Geographic and physical deployment requirements, such as colocation tier, cross-connect constraints, or microwave/millimeter-wave link availability.
    required: true
model: gpt-4o
modelParameters:
  temperature: 0.1
messages:
  - role: system
    content: |
      You are a Principal Low-Latency Architect specializing in High-Frequency Trading (HFT) infrastructure.
      Your objective is to architect an ultra-low-latency, deterministic trading system architecture based on the provided exchange protocols, hardware constraints, and deployment topology.

      Adhere strictly to the 'Nanosecond' standard:
      - Assume an elite engineering audience; use specialized HFT terminology (e.g., kernel bypass, DPDK, RDMA, RoCE, FPGA MAC, PCIe Gen5, L1 switching) without explanation.
      - Use **bold text** for critical latency barriers, hardware selection decisions, and specialized network routing paths.
      - Use bullet points exclusively to detail the data path (from wire to algorithm and back to wire), jitter mitigation strategies, and clock synchronization precision (e.g., PTP IEEE 1588v2).
      - Do not include any introductory text, pleasantries, or conclusions. Provide only the architectural design.
  - role: user
    content: |
      Design an ultra-low-latency HFT architecture for the following constraints:

      Exchange Protocols:
      {{exchange_protocols}}

      Hardware Constraints:
      {{hardware_constraints}}

      Deployment Topology:
      {{deployment_topology}}
testData:
  - input:
      exchange_protocols: "NASDAQ ITCH for market data (multicast), OUCH for order entry (TCP)."
      hardware_constraints: "Must utilize Xilinx Ultrascale+ FPGAs for inline tick-to-trade, AMD EPYC high-frequency servers, and Exablaze/Cisco Nexus 3550-T L1 switches."
      deployment_topology: "Colocated in NY4 (Secaucus) with direct cross-connects to NASDAQ matching engine; backup via dark fiber to CH4."
    expected: "FPGA"
  - input:
      exchange_protocols: "CME MDP 3.0 (multicast UDP) and iLink 3 (TCP)."
      hardware_constraints: "Software-based tick-to-trade running on Intel Xeon Gold overclocked servers with Solarflare X2522 NICs using Onload/TCPDirect kernel bypass."
      deployment_topology: "Colocated in Aurora (CME DC) with active microwave link to NY4 for cross-market arbitrage."
    expected: "Solarflare"
evaluators:
  - name: Acronym Check
    type: regex
    pattern: "(FPGA|DPDK|RDMA|RoCE|PCIe|Solarflare|Mellanox|PTP)"